Bruce Jacob

University of Maryland Exascale Systems Research

University of Maryland Memory-Systems Research

Keystone Professor, Full Professor
Department of Electrical & Computer Engineering
University of Maryland at College Park
College Park, MD 20742

E-mail: email address


MEMSYS: The International Symposium on Memory Systems

Spring 2021: ENEE 447, Operating Systems
Office Hours: none until the campus opens back up

Office: 1333 A.V. Williams, 8223 Paint Branch Dr.
Phone: +1 301-405-0432
Fax: +1 301-314-9281

Research Areas - Jacob's current work is in the area of systems architecture for high-performance computing (solving the exascale problem), and memory systems design. He currently designs system architectures and memory-systems architectures for industry and DOE supercomputer labs.

Forward ... A Foreword - I was invited to write the Foreword for the Intel Technology Journal special issue on Memory Systems and Memory Resiliency. This does a decent job of putting memory issues into focus and correct context, as we move forward into ever-larger computer systems.

Curriculum Vitae and Bios

Attention Students - including information on RA positions and Scholarly Papers


  • A.B. (Mathematics, cum laude) Harvard University - Cambridge MA, 1988
  • M.S. (Computer Science & Engineering) University of Michigan - Ann Arbor MI, 1995
  • Ph.D. (Computer Science & Engineering) University of Michigan - Ann Arbor MI, 1997

Industry Experience

Computational Artifacts

Honors & Awards

  • Named Fellow, IEEE, effective 1 January 2021, "for contributions to computer memory design and analysis"
  • University of Maryland "Research Leader," 2017
  • University of Maryland "Research Leader," 2016
  • University of Maryland "Research Leader," 2012
  • Full Professorship Awarded, 2011
  • University of Maryland "Research Leader," 2010
  • Clark School of Engineering Keystone Professor, 2006
  • University of Maryland "Research Leader," 2006
  • University of Maryland "Rainmaker," 2005
  • IBM Shared University Research Award, 2005
  • University of Maryland Award for Teaching Excellence, 2004
  • Tenure Awarded, 2003
  • University of Maryland "Rainmaker," 2001
  • National Science Foundation CAREER Award, 2000
  • ECE Department George Corcoran Award, 1999

Research Interests

University of Maryland Memory-Systems Research

  • Overview & FAQ
  • Computational artifacts
  • Workloads and their characterization
  • The many, many studies

Research Group: Grad Students, 2003 Grad Students, 2006

Recent Invited Talks

    2020 Multicore World
    • Whither External Memory? Invited Talk, SRC/SIA/DOE Decadal Plan for Semiconductors: New Trajectories for Memory and Storage Technologies, Fall 2020.
    • DRAMsimL -- Current Issues in Its Development. Invited Talk, DOE Brainstorming Workshop on Machine Learning for Modeling and Simulation, Summer 2020.
    • Machine Learning is the Holy Grail of Memory-System Modeling & Simulation. Panelist Talk, Modeling & Simulation of Systems and Applications (ModSim), Summer 2020.
    2019 ModSim
    • All Tomorrow's Memories. Invited Seminar, University of Texas at Austin, Department of Electrical & Computer Engineering, Austin TX. Winter 2019.
    2018 MCHPC Keynote
    • Modeling Tomorrow's Memory Systems. Invited Talk, Modeling & Simulation of Systems and Applications (ModSim), Seattle WA. Summer 2018.
    2017 EMS Keynote
    • Tomorrow's Memory Systems, 2017 Edition. Keynote, DATE Workshop on on Emerging Memory Solutions, Lausanne, Switzerland. Spring 2017.
    • Modeling Tomorrow's Memory Systems. Invited Talk, Modeling & Simulation of Systems and Applications (ModSim), Seattle WA. Summer 2017.
    • Tomorrow's Memory Systems, 2017 Edition. Computer Science & Engineering Department, Texas A&M University, College Station TX. Spring 2017.
    2016 TAMU Eminent Scholar
    • A Couple Decades of Hardware/Software Co-Optimization. Computer Engineering Eminent Scholar Seminar Series, Texas A&M University, College Station TX. Fall 2016.
    DOE Roadmap
    • Execution Models and the Memory System. Computing 2025 and Beyond, Argonne National Laboratory, Lemont IL. Summer 2016.
      One of a dozen members of academia and industry invited to participate with DOE in creating a roadmap for computer science and applied mathematics research at DOE in the coming decades.
    Salishan Invitation
    • Exascale Begins at the Memory System. Invited Talk, Salishan Conference on High-Speed Computing, Gleneden Beach OR. Spring 2016.
    EMS Keynote
    • Exascale Begins at the Memory System. Keynote, DATE Workshop on on Emerging Memory Solutions, Dresden, Germany. Spring 2016.
    2015 ModSim Keynote
    • Tomorrow's High-Bandwidth, High-Capacity, Low-Power Memory Systems. Keynote, Modeling & Simulation of Systems and Applications (ModSim), Seattle WA. Fall 2015.
    HMC Workshop Talk
    • Some of Our Work on Hybrid Memory Cube. Invited Talk, Workshop on Hybrid Memory Cube, Fort Meade MD. Fall 2015.
    2014 SAMOS Keynote
    • Next-Generation Memory Systems. Keynote, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Samos Island, Greece. Summer 2014.
    Computing Frontiers Keynote
    • High-Bandwidth, High-Capacity, Low-Power Memory Systems. Keynote, ACM International Conference on Computing Frontiers, Cagliari, Italy. Spring 2014.
    University of Cyprus
    2013 FORTH
    • (Exascale) Data Movement. Foundation for Research and Technology (FORTH), Heraklion (Crete), Greece. Winter 2013.
    University of Cyprus
    • (Exascale) Data Movement. University of Cyprus, Nicosia, Cyprus. Winter 2013.
    2012 Energy Secretary
    • Data Access, Data Movement, Data Integrity. Roughly twenty members of academia, industry, and the national laboratories were asked to brief Secretary Chu on the status of supercomputing today and what is required to achieve exascale performance in the near future. Spring 2012.
    Int'l Supercomputing
    • Big Memories. Invited Keynote, Session on "Large Memory Systems & Challenges." International Supercomputing Conference (ISC '12), Hamburg, Germany. Spring 2012.
    2010 Careers in ECE
    Int'l Supercomputing
    • Memory Systems Then, Now, and To Come. Invited Keynote, Session on "New Memory and Storage Hierarchies for HPC - Opportunities and Challenges." International Supercomputing Conference (ISC '10), Hamburg, Germany. Spring 2010.
    WAMT 2010
    • Thoughts on Memory. (WAMT panel response to question what is/are the memory system's biggest problem/s and its/their solution/s? ...) Invited talk, Workshop on Architecting Memory Technologies. Pittsburgh PA. Spring 2010.
    2009 ECE Advisory
    Clark School
    Board of Visitors
    2008 National Student
    Leadership Conference
    2007 National Academies
    • Memory Systems. National Academies CSTB Briefing: Trends in Computing Performance, an NRC-organized panel, Mountain View CA. Fall 2007.
      One of fifteen people across all areas of computing (including sub-disciplines of Storage, Power, Programming, and Applications) invited to brief a National Academies committee on the state of affairs in our various sub-disciplines. Briefers were asked to inform the committee on the technical issues and present/future trends that can hinder or aid the continued growth of computer performance. This resulted in a widely cited NRC report, The Future of Computing Performance: Game Over or Next Level?

Selected Publications

All Publications

All Talks & Presentations

Students: Awards/Honors, Research Topics, and Theses

    Student Honors:
    Elizabeth Kenyon
    • Philip Merrill Presidential Scholar, October 2009.
    Aamer Jaleel
    • Award for Best Paper Presentation, 11th International Symposium on High Performance Computer Architecture (HPCA 2005), February 2005.
    Christine Smit
    • Chosen to be Student Speaker at University of Maryland Campus-Wide Commencement, May 20th, 2004.
    Sandy Klemm
    • 2002 Merit Fair First Place Winner for his undergraduate research on dynamic voltage scaling.

    Current Students:
    Lu-Yi Kang
    • Nonvolatile memory systems and their control.
    Brendan Sheehy
    • Next-generation DRAM systems.
    Jim Stevens
    • Operating systems impications for non-volatile main memories.

    Ph.D. Theses:
    Meenatchi Jagasivamani
    • Ph.D. 2020. Resistive RAM Based Main-Memory Systems: Understanding the Opportunities, Limitations, and Tradeoffs (Northrop Grumman)
      As DRAM faces scaling issues as a high-density memory, emerging technologies are being explored as alternatives. Resistive Memories (ReRAM) are scalable, vertically stackable, and can deliver higher density than DRAM as a main-memory solution. This research work explores ReRAM as a main-memory alternative at three levels of detail: at the device level, at the physical-design level, and finally at the architecture level. Cells are fabricated and characterized; reduced write energies can extend cell lifetimes, and system-level simulations show that, for high core counts, this offers a better main-memory alternative than any other existing memory technology.
    Shang Li
    • Ph.D. 2019. Scalable and Accurate Memory System Simulation (Cadence Design Systems)
      We develop a fast and validated cycle accurate main memory simulator that can accurately model almost all existing DRAM protocols and some NVM protocols, and it can be easily extended to support upcoming protocols as well. To efficiently simulate the increasingly paralleled memory systems, we propose a lax synchronization model that allows efficient parallel DRAM simulation. Lastly, we discuss the limitation of cycle accurate models, and explore the possibility of alternative modeling of DRAM. We propose a novel approach that converts DRAM timing simulation into a classification problem. By doing so we can make predictions on DRAM latency for each memory request upon first sight, which makes it compatible for scalable architecture simulation frameworks.
    Paul Tschirhart
    • Ph.D. 2015. Multi-Level Main Memory Systems: Technology Choices, Design Considerations, and Trade-off Analysis. (Northrop Grumman)
      Multi-level main memory systems provide a way to leverage the advantages of different memory technologies to build a main memory that overcomes the limitations of the current flat DRAM-based architecture, using any of the new non-volatile technologies that have appeared in the past decade. However, these novel technologies require multi-level main memory hierarchies to achieve acceptable performance. This dissertation investigates the implications of these new multi-level main memory architectures and provides key insights into the trade-offs associated with the technology and organization choices that are integral to their design.
    Paul Rosenfeld
    • Ph.D. 2014. Performance Exploration of the Hybrid Memory Cube. (Micron)
      The Hybrid Memory Cube (HMC) is an emerging main memory technology that leverages advances in 3D fabrication techniques to create a memory device with several DRAM dies stacked on top of a CMOS logic layer. The logic layer at the base of each stack contains several DRAM memory controllers that communicate with the host processor over high speed serial links using an abstracted packet interface. While the architecture of this type of device is still nascent, we present several parameter sweeps to highlight the performance characteristics and design trade-offs.
    Ishwar Bhati
    • Ph.D. 2014. Scalable and Energy-Efficient DRAM Refresh Techniques. (Oracle/Sun)
      A DRAM cell requires periodic refresh operations to preserve data in its leaky capacitor. Previously, the overheads of refresh operations were insignificant, but, as both the size and speed of DRAM chips have increased significantly in the past decade, refresh has become a dominating factor of both DRAM performance and power dissipation. This dissertation presents a comprehensive study of the issues related to refresh operations in modern DRAM devices, and it then proposes techniques to mitigate refresh penalties.
    Mu-Tien Chang
    • Ph.D. 2013. Technology Choices for Large Last-Level Caches. (Samsung)
      Several memory technologies, including SRAM, STT-RAM (MRAM), and embedded DRAM (eDRAM), have been used to implement Large last-level caches (L3Cs). This thesis compares their characteristics and performance: SRAM is relatively low density and dissipates high leakage; STT-RAM has long write latency and requires high write energy; eDRAM requires refresh. As future processors are expected to have larger last-level caches, the objective of this dissertation is to study the tradeoffs associated with using each.
    Elliott Cooper-Balis
    • Ph.D. 2012. Buffer-On-Board Memory Systems. (Micron)
      A recent trend places intermediate logic between the CPU and DRAM, communicating with the CPU over a fast and narrow bus. reducing pin-out to the memory system and increasing signal integrity to the DRAM, thereby allowing faster clock rates while maintaining capacity. Our study of this design space investigates optimal use of the resources involved, including DRAM and bus organization, queue storage, and mapping schemes.
    Cagdas Dirik
    • Ph.D. 2009. Performance Analysis of NAND Flash Memory Solid-State Disks (SSDs) (SanDisk)
      NAND Flash Solid State Disks (SSDs) are becoming an increasingly attractive alternative to Hard Disk Drives (HDDs). It is important to understand the internals of solid state disk drives. This work provides an in-depth study of the relationship between SSD architectures, their management algorithms, and system-level performance, as well as proposing new optimization heuristics.
    Sadagopan Srinivasan
    • Ph.D. 2007. Prefetching vs. the Memory System: Optimizations for Multi-core Server Platforms. (Intel)
      Investigates prefetching scheme for servers with respect to realistic memory systems. Real systems disable prefetching in server settings, suggesting that there is a fundamental disconnect between research and practice. This thesis shows that the disconnect is due to the use of simplistic memory models; experimental results suggest that using simplistic models can mis-predict the system performance by a factor of two.
    Brinda Ganesh
    • Ph.D. 2007. Understanding and Optimizing High-Speed Serial Memory-System Protocols. (Intel)
      Next-generation memory systems such as the Fully-Buffered DIMM use a system topology more akin to a computer network than a traditional memory bus. Data movement in these systems is complicated by the bus organization, making it essential to understand the implications when designing schedulers for these systems.
    Ankush Varma
    • Ph.D. 2007. High-Speed Performance, Power, and Thermal Co-Simulation for SoC Design. (Intel)
      Developing tools and methodologies for fast, accurate, high-level power and thermal modeling on SoCs. Exploring power/thermal modeling for MEMS, mixed-signal and digital SoC components, how these models can be built into high-level System Description Languages (such as SystemC), and how high-level power models can be made robust to low-level design decisions.
    Nuengwong (Ohm) Tuaycharoen
    Samuel Rodriguez
    • Ph.D. 2006. myCACTI: A New Cache-Design Tool for Pipelined Nanometer Caches. (AMD)
      This dissertation shows that both CACTI and eCACTI still contain major limitations and even flaws in their design, making them unsuitable for use in very-deep submicron and nanometer caches, especially pipelined designs. These limitations and flaws are discussed in detail. This dissertation then introduces a new tool, called myCACTI, that addresses all these limitations and, in addition, introduces major enhancements to the simulation framework.
    Aamer Jaleel
    • Ph.D. 2005. The Effects of Out-of-Order Execution on the Memory System. (Intel)
      Studies the deleterious effects of out-of-order execution. Common wisdom holds that bigger is better: to wit, the larger the instruction window, the better the performance. Numerous studies show this result, and, consequently, numerous other studies investigate low-cost ways to implement large instruction windows. This study shows that, once one includes a realistic model of the memory system, nearly all of those projected performance gains fail to materialize.
    David Tawei Wang
    Brian Davis
    • Ph.D. 2001. Modern DRAM Architectures. (Michigan Tech)
      This thesis examines a variety of modern DRAM architectures in the context of current desktop workstations. The DRAM examined (EDO, Burst EDO, SDRAM, DDR, DDR2, Rambus, ESDRAM, FCRAM, VCM) include those which are available today, as well as a number of architectures which are expected to come to market in the near future. (co-advised by Trevor Mudge)

    M.S. Theses:
    Jeffrey Scott Smith
    Rami Nasr
    Amol Gole
    Bharath Iyer
    Nuengwong (Ohm) Tuaycharoen
    Lei Zong
    Brinda Ganesh
    Aamer Jaleel
    Paul Kohout
    Tiebing Zhang
    Christopher Collins

Past, Present, and Future Classes

Old Research Areas

DRAM Systems Research

Embedded Systems Research

Circuit Integrity Research

Research in Memory Management and Virtual Memory

The RiSC-16

Fun Stuff from Long Ago (and Far Away)

Photo: Marcus Yam, Washington Post
The Chuck Berry of the Engineering World, Susan Kinzie, Washington Post, July 7, 2009. Front page of the Metro section.


The Gig-Saver: 15 Tones, One Guitar, Interview with Robert Siegel on "All Things Considered," National Public Radio (NPR), July 10, 2009.
Awesome quote from Siegel: "In these hard times, why go buy five new electric guitars when you can buy one?"
You can listen to the audio of the radio segment here:


WTOP interview, July 8, 2009.
You can listen to the audio of the radio segment here:

Brief video from WTOP:


WUSA TV interview, July 8, 2009.

"Putting More Sexy In Your Guitar," Bruce Leshan, WUSA TV9, July 8, 2009.

Last updated: recently by Bruce Jacob (email address) using the vi text editor ... best viewed in Safari