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Bruce Jacob
University of Maryland Exascale Systems Research
University of Maryland Memory-Systems Research
Keystone Professor, Full Professor
E-mail: <>< |
Spring 2021:
ENEE 447, Operating Systems
Office Hours: none until the campus opens back up
Office: 1333 A.V. Williams, 8223 Paint Branch Dr.
Phone: +1 301-405-0432
Fax: +1 301-314-9281
Education
Industry Experience
Computational Artifacts
Honors & Awards
Research Interests
University of Maryland Memory-Systems Research
Research Group:
Grad Students, 2003
Grad Students, 2006
Recent Invited Talks
Selected Publications
And, by the way, yes -- we are the group who did the performance modeling of Hybrid Memory Cube for Micron, while
the part was in development (Paul and Elliott were grad students at the time,
and Dave Resnick, the man behind HMC's design, was at Micron).
The first paper in the list is about that -- and, yes, they are accurate results, because
our simulator reflects how the part is actually built.
We tried submitting that paper to several computer architecture conferences,
but the paper was rejected for two reasons: first, the work was considered "not novel" (we couldn't publish
anything until Micron announced HMC details in 2012, and evidently, the moment Micron announced it,
it became "not novel"), and, secondly, the program committees really, really, REALLY wanted power numbers.
Which we couldn't produce, and still can't, because of NDA reasons.
Enjoy!
Clicking the link above or the image of the cover should take you to the Morgan-Clypool website.
Or you can always get hardcopy from Amazon.com.
Approx. 1000 pages and half a million words according to Translator's Abacus.
PDF for several parts of the book:
Clicking the link above or the image of the cover should take you to the Morgan Kaufmann website,
where you can get yourself one of these rare beauties.
Alternatively:
check it out on Amazon.com,
or save a few bucks and get it
on Alibris.
Students: Awards/Honors, Research Topics, and Theses
Past, Present, and Future Classes
Old Research Areas
Research in Memory Management and Virtual Memory
Fun Stuff from Long Ago (and Far Away)
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The Gig-Saver: 15 Tones, One Guitar,
Interview with Robert Siegel on "All Things Considered," National Public Radio (NPR), July 10, 2009.
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WTOP interview, July 8, 2009.
Brief video from WTOP:
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WUSA TV interview, July 8, 2009.
"Putting More Sexy In Your Guitar," Bruce Leshan, WUSA TV9, July 8, 2009.
Forward ... A Foreword
-
I was invited to write the Foreword for the Intel Technology Journal special issue on Memory Systems and Memory Resiliency.
This does a decent job of putting memory issues into focus and correct context, as we move forward into ever-larger computer systems.
Curriculum Vitae and Bios
Attention Students
- including information on RA positions and Scholarly Papers
(now part of Comverse Network Systems [who seem to have changed their name
to Comverse Technology {and now just 'Comverse'}])
(now part of LHS Group
[which is actually now part of Sema Group
{which seems to be part of Schlumberger at this point ... I'm losing track}])
(and, as of 2004, they're part of uReach Technologies
... I think I will give up on keeping this up-to-date)
2020
Multicore World
SRC/SIA/DOE
ModSim
ModSim
2019
ModSim
UTAustin
2018
MCHPC
Keynote
ModSim
2017
EMS
Keynote
ModSim
TAMU
2016
TAMU Eminent Scholar
DOE Roadmap
One of a dozen members of academia and industry invited to participate with DOE in creating a roadmap for
computer science and applied mathematics research at DOE in the coming decades.
Salishan
Invitation
EMS
Keynote
2015
ModSim
Keynote
HMC Workshop
Talk
2014
SAMOS
Keynote
Computing Frontiers
Keynote
University
of Cyprus
2013
FORTH
University
of Cyprus
2012
Energy Secretary
Briefing
Int'l Supercomputing
Conference
2010
Careers in ECE
Int'l Supercomputing
Conference
WAMT 2010
Sun-DARPA UNIC
Workshop
2009
ECE Advisory
Board
Clark School
Board of Visitors
ACACES
2008
National Student
Leadership Conference
2007
National Academies
Briefing
One of fifteen people across all areas of computing (including sub-disciplines of Storage, Power, Programming, and
Applications) invited to brief a National Academies committee on the state of affairs in our various
sub-disciplines. Briefers were asked to inform the committee on the technical issues and present/future trends
that can hinder or aid the continued growth of computer performance. This resulted in a widely cited NRC report,
The Future of Computing Performance: Game Over or Next Level?
2020
IEEE CAL
COOL Chips
2019
IEEE Micro
POMACS
MEMSYS
Note: this is an initial description of our next-generation simulator, DRAMsimL.
This represents the first time someone has built a
machine-learning-based DRAM simulator, in which the simualtor need not maintain a
cycle-accurate state and instead returns a highly accurate "hint" about latency.
This means that CPU simulators can be rewritten as VERY simple (no longer need to
keep polling until the memory controller returns the result), and it makes massively
parallel systems MUCH faster to simulate.
See also the ModSim 2019 presentation
and Shang Li's thesis.
MEMSYS
MEMSYS
2018
MEMSYS
MEMSYS
MEMSYS
HPCC
2017
MEMSYS
2016
IEEE-TC
MEMSYS
MEMSYS
2015
ISCA
IEEE CAL
IEEE CAL
MEMSYS
2014
TECH
REPORTS
We have been submitting the following papers to various architecture conferences for the past few years,
to no avail. It's about time to give up and put them out as tech reports, because it's good research.
The work was not done in 2014, that is simply when I decided to make them public.
Each tech report has the date appropriate to the timeframe of the work and when the work was written up.
[HMC]
[NVMM]
[harsh chip]
2013
ISLPED
HPCA
ITJ
2012
ISCA
MASCOTS
[HMC]
2011
IEEE CAL
MSPC
2010
IEEE Micro
Technology
Management
[NVMM]
2009
ISCA
Morgan
Claypool
book
MoBS
2008
TECS
MoBS
2007
Open letter
Morgan
Kaufmann
book
(now Elsevier)
HPCA
TECS
2006
CASES
ISLPED
HPCA
E&M
IEEE-TC
2005
HPCA
ISPASS
SIGARCH
ASP-DAC
MSP
2004
ISCA
EMC
JSSE
[harsh chip]
2003
CASES
CODES+ISSS
IEEE-TC
IEEE Micro
2002
TECS
2001
ISCA
CASES
CASES
IEEE-TC
IEEE-TC
1999
ISCA
CASES
This paper gives a fully associative architecture for a software-managed cache design.
1998
ASPLOS
IEEE Micro
IEEE Computer
CASES
The slides for the talk are available on-line in PDF format,
and include details not found in the 2-page abstract.
1997
HPCA
1996
Organised Sound
IEEE-TC
1995
ICMC
Student Honors:
Elizabeth Kenyon
Aamer Jaleel
Christine Smit
Sandy Klemm
Current Students:
Lu-Yi Kang
Brendan Sheehy
Jim Stevens
Ph.D. Theses:
Meenatchi Jagasivamani
As DRAM faces scaling issues as a high-density memory, emerging
technologies are being explored as alternatives.
Resistive Memories (ReRAM) are scalable, vertically stackable, and can deliver higher
density than DRAM as a main-memory solution.
This research work explores ReRAM as a main-memory alternative at three levels of detail:
at the device level, at the physical-design level, and finally at the architecture level.
Cells are fabricated and characterized; reduced write energies can extend cell lifetimes,
and system-level simulations show that, for high core counts, this offers a better
main-memory alternative than any other existing memory technology.
Shang Li
We develop a fast and validated cycle accurate main memory simulator that can accurately model
almost all existing DRAM protocols and some NVM protocols, and it can be easily extended to
support upcoming protocols as well.
To efficiently simulate the increasingly paralleled memory systems,
we propose a lax synchronization model that allows efficient parallel DRAM simulation.
Lastly, we discuss the limitation of cycle accurate models, and explore the possibility of
alternative modeling of DRAM. We propose a novel approach that converts DRAM timing simulation
into a classification problem. By doing so we can make predictions on DRAM latency for each memory
request upon first sight, which makes it compatible for scalable architecture simulation
frameworks.
Paul Tschirhart
Multi-level main memory systems provide a way to leverage the advantages of different memory technologies to build a
main memory that overcomes the limitations of the current flat DRAM-based architecture, using any of the new
non-volatile technologies that have appeared in the past decade. However, these novel technologies
require multi-level main memory hierarchies to achieve acceptable performance. This dissertation investigates the
implications of these new multi-level main memory architectures and provides key insights into the trade-offs
associated with the technology and organization choices that are integral to their design.
Paul Rosenfeld
The Hybrid Memory Cube (HMC) is an emerging main memory technology that leverages advances in 3D fabrication
techniques to create a memory device with several DRAM dies stacked on top of a CMOS logic layer.
The logic layer at the base of each stack contains several DRAM memory controllers that communicate with the
host processor over high speed serial links using an abstracted packet interface.
While the architecture of this type of device is still nascent, we present several
parameter sweeps to highlight the performance characteristics and design trade-offs.
Ishwar Bhati
A DRAM cell requires periodic refresh operations to preserve data in its leaky capacitor. Previously, the
overheads of refresh operations were insignificant, but, as both the size and speed of DRAM chips have
increased significantly in the past decade, refresh has become a dominating factor of both DRAM performance and
power dissipation. This dissertation presents a comprehensive study of the issues
related to refresh operations in modern DRAM devices, and it then proposes techniques to mitigate refresh
penalties.
Mu-Tien Chang
Several memory technologies, including SRAM, STT-RAM (MRAM), and embedded DRAM (eDRAM), have been
used to implement Large last-level caches (L3Cs). This thesis compares their characteristics and performance:
SRAM is relatively low density and dissipates high leakage; STT-RAM has long write latency and requires high
write energy; eDRAM requires refresh. As future processors are expected to have larger last-level caches,
the objective of this dissertation is to study the tradeoffs associated with using each.
Elliott Cooper-Balis
A recent trend places intermediate logic between the CPU and DRAM,
communicating with the CPU over a fast and narrow bus.
reducing pin-out to the memory system and increasing signal integrity to the DRAM,
thereby allowing faster clock rates while maintaining capacity.
Our study of this design space investigates
optimal use of the resources involved, including DRAM and bus organization,
queue storage, and mapping schemes.
Cagdas Dirik
NAND Flash Solid State Disks (SSDs) are becoming an increasingly attractive alternative to Hard Disk Drives (HDDs).
It is important to understand the internals of solid state disk drives. This work provides an in-depth study of
the relationship between SSD architectures, their management algorithms, and system-level performance, as well as
proposing new optimization heuristics.
Sadagopan Srinivasan
Investigates prefetching scheme for servers with respect to realistic
memory systems. Real systems disable prefetching in server settings,
suggesting that there is a fundamental disconnect between research and practice.
This thesis shows that the disconnect is due to the use of simplistic
memory models; experimental results suggest that using
simplistic models can mis-predict the system performance by a factor of two.
Brinda Ganesh
Next-generation memory systems such as the Fully-Buffered DIMM use a system
topology more akin to a computer network than a traditional memory bus.
Data movement in these systems is complicated by the bus organization,
making it essential to understand the implications when designing schedulers
for these systems.
Ankush Varma
Developing tools and methodologies for fast, accurate, high-level power and thermal
modeling on SoCs.
Exploring power/thermal modeling for MEMS, mixed-signal and digital SoC components,
how these models can be built into high-level System Description Languages (such as SystemC),
and how high-level power models can be made robust to low-level design decisions.
Nuengwong (Ohm) Tuaycharoen
SYSim is a full-system simulator that integrates Bochs, Wattch, DRAMsim, and DiskSim, boots Linux,
and enables complete memory hierarchy studies in both performance and power consumption domains.
With it, we investigate the system-level impacts of disk- and DRAM-system technologies
such as DRAM capacity, disk caching, disk speed, etc.
Samuel Rodriguez
This dissertation shows that both CACTI and eCACTI still contain major
limitations and even flaws in their design, making them unsuitable for use in very-deep submicron and
nanometer caches, especially pipelined designs. These limitations and flaws are discussed in detail.
This dissertation then introduces a new tool, called myCACTI, that addresses all these limitations and,
in addition, introduces major enhancements to the simulation framework.
Aamer Jaleel
Studies the deleterious effects of out-of-order execution.
Common wisdom holds that bigger is better: to wit, the larger the instruction window, the better
the performance. Numerous studies show this result, and, consequently, numerous other studies
investigate low-cost ways to implement large instruction windows. This study shows that, once one
includes a realistic model of the memory system, nearly all of those projected
performance gains fail to materialize.
David Tawei Wang
An in-depth treatment of modern, power-limited, DRAM systems.
The timing parameters tFAW and tRRD, introduced at the DDR2 generation of DDRx SDRAM, have a
deleterious effect on system-level performance, significantly limiting sustainable bandwidth.
The work characterizes the problem and provides a scheduling algorithm that offers a solution.
As of February 2008,
MetaRAM is now radar-visible.
Fred, Dave, and Co. are set to take over the world.
Brian Davis
This thesis examines a variety of modern DRAM architectures
in the context of current desktop workstations. The DRAM examined
(EDO, Burst EDO, SDRAM, DDR, DDR2, Rambus, ESDRAM, FCRAM, VCM)
include those which are available today, as well as a number of architectures which are
expected to come to market in the near future.
(co-advised by Trevor Mudge)
M.S. Theses:
Jeffrey Scott Smith
Rami Nasr
Amol Gole
Bharath Iyer
Nuengwong (Ohm) Tuaycharoen
Lei Zong
Brinda Ganesh
Aamer Jaleel
Paul Kohout
Tiebing Zhang
Christopher Collins
Photo: Marcus Yam, Washington Post
The Chuck Berry of the Engineering World,
Susan Kinzie, Washington Post, July 7, 2009. Front page of the Metro section.
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Awesome quote from Siegel: "In these hard times, why go buy five new electric guitars when you can buy one?"
You can listen to the audio of the radio segment here:
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You can listen to the audio of the radio segment here:
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