DRAM die/chip

The RiSC-16 Architecture

Bruce Jacob

email address

The RiSC-16 is a teaching instruction-set used by the author at the University of Maryland, and which is a blatant (but sanctioned) rip-off of the Little Computer (LC-896) developed by Peter Chen at the University of Michigan. The primary differences include the following:

RiSC stands for Ridiculously Simple Computer, which makes sense in the context in which the instruction-set is normally used -- to teach simple organization and architecture to undergraduates who do not yet know how computers work. The architecture has a whopping 8 opcodes, uses 8 registers, and is nonetheless general enough to execute fairly sophisticated programs. This makes it a relatively useful teaching tool, as it allows students to look at computer architecture concepts from simple to advanced without the instruction-set getting in the way or cluttering up the picture.

This page includes documentation on the instruction set and several different processor implementations, including sequential, pipelined, and out-of-order. Verilog for the out-of-order core is also available for download. Verilog for the other implementations is not available, because those are projects that I assign to my architecture students.

PDF Documents:

Source Code:

If you do not find what you are looking for, please feel free to email me with suggestions for more/different/modified documents. Same goes for bug fixes.