ENEE244-02xx: Digital Logic Design
Syllabus (includes grading policy) | Lecture Summaries
| Homeworks |
| Textbook | Office Hours
Final Exam information is now up here.
Homework 9 is up, due in class on Dec. 11.
This course covers switching algebra and its use in design with logic gates, flip-flops, registers and counters, and the
analysis of these networks. Also covered are Karnaugh map simplification of gate networks, design and analysis of synchronous sequential systems,
implementation with PLA's, multiplexers, decoders, encoders, binary arithmetic units such as adders and subtractors, conversions between
decimal and arbitrary radix numbers, especially octal, hexadecimal, and binary representations, radix and diminished radix arithmetic,
and character codes.
- This course meets on TuTh 2:00pm-3:15pm in CHE 2118.
There are no prerequisites for this course but students must
have a Sophomore standing or higher.
- Section 201: M 9-9:50am in CHE 2140
- Section 202: M 11-11:50am in EGR 3111
- Section 203: M 12-12:50pm in EGR 3111
- Section 204: M 1-1:50pm in EGR 3111
- Tentative midterm exams dates/times: In class on September 30, October 28, November 25.
- Final exam date/time/place: TBD.
The TA for this course is Shang Li (email: shawn dot li dot x
jtu at gmail dot com).
The UTFs for this course are:
Max DePalma (email: m dot d dot depalma at gmail dot com) for Sections 201, 202 and
Jordan Appler (email: jordanappler at gmail dot com) for Sections 203, 204.
"Digital Principles and Design" by Donald D. Givone, McGraw-Hill 2003.
Instructor office hours: T 10am-11am, R 11am-12pm 3407 A.V. Williams
TA office hours: W 11am-12pm 1143 A.V. Williams
UTF office hours for Sections 201, 202: M 10-11am, 12-1pm 1369 AVW
UTF office hours for Sections 203, 204: M 2-3pm, W 12-1pm 1369 AVW
All students are presumed to be aware of the UMD policy on academic integrity.