Final Exam
ENEE24402xx: Digital Logic Design
Fall 2014 Final Exam Info
The Final Exam will be held on Thursday, Dec. 18 from 10:30am12:30pm in CHE 2118. It will consist of 10 problems (some with multiple parts). The exam is **cumulative** and will cover material from the entire semester, with emphasis on material since the last exam (Lectures 2629).
There will be a review session on Friday, Dec. 12 from 11am12:15pm in AVW 2120.
Shang will go over the solutions of the following problems and in addition will set aside time for answering questions:
Exercises 7.15; 7.18; 7.19; 7.21; 7.24.
Here are a list of topics from Lectures 2629 **only**:

Structure and operation o fclocked synchronous sequential networks: Current state, next state, Mealy versus Moore.

Analysis of clocked synchronous sequential networks: Excitation and output expressions, transition equations, transition tables, excitation tables, state tables, state diagrams, network terminal behavior, false outputs in Mealy networks.

Modeling clocked synchronous sequential behavior: Constructing state diagrams from a description of the functionality of the network.

State table reduction: Determining equivalent pairs of states, obtaining the equivalence classes of states, constructing a minimal state table.

The state assignment problem: Simple guidelines for obtaining state assignments, stateassignment map, unused states.

Completing the design of clocked synchronous sequential networks: Application tables, transition table to excitation table, using Kmaps for final circuit design, realizations using programmable logic devices.