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University of Maryland
Exascale Systems Research: Computational Artifacts

Bruce Jacob - email address - http://www.ece.umd.edu/~blj/

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Computational Artifacts

Our research group has developed and released several simulation frameworks, one of which has become very widely used (see
www.ece.umd.edu/DRAMsim for our public-domain DRAM-system simulator, now used within Intel, IBM, Cray, and numerous academic research groups).

The following artifacts are described herein:

Note that all of our publicly released code can be found in SST: Tthe Structural Simulation Toolkit.

NVsim: A hybrid, multi-level memory simulator

As computer systems evolve towards exascale and attempt to meet new application requirements such as big data, conventional memory technologies and architectures are no longer adequate in terms of bandwidth, power, capacity, or resilience. In order to understand these problems and analyze potential solutions, an accurate simulation environment that captures all of the complex interactions of the modern computer system is essential. In this work, we present an integrated simulation infrastructure for the entire memory hierarchy, including the processor cache, the DRAM main memory system, and nonvolatile memory, whether it is integrated as hybrid main memory or as a solid state drive. The memory simulations we present are integrated into a full system simulation, which enables studying the memory hierarchy with a faithful representation of a modern x86 multicore processor. The simulated hardware is capable of running unmodified operating systems and user software, which generates authentic memory access patterns for memory hierarchy studies. To demonstrate the capabilities of our infrastructure we include a series of experimental examples that utilize the cache, DRAM main memory, and nonvolatile memory modules. The simulator is described in the following article:

DRAMsim: A memory-system simulator

As memory accesses become slower with respect to the processor and consume more power with increasing memory size, the focus of memory performance and power consumption has become increasingly important. With the trend to develop multi-threaded, multi-core processors, the demands on the memory system will continue to scale. However, determining the optimal memory system configuration is non-trivial. The memory system performance is sensitive to a large number of parameters. Each of these parameters take on a number of values and interact in fashions that make overall trends difficult to discern. A comparison of the memory system architectures becomes even harder when we add the dimensions of power consumption and manufacturing cost. Unfortunately, there is a lack of tools in the public-domain that support such studies. Therefore, we have built and made publicly available DRAMsim, a detailed and highly configurable C-based memory system simulator to fill this gap. DRAMsim implements detailed timing models for a variety of existing memories, including SDRAM, DDR, DDR2, DRDRAM and FB-DIMM,with the capability to vary their parameters easily. It also models the power consumption of SDRAM and its derivatives. It can be used as a stand-alone simulator or as part of a more comprehensive system-level model. We have successfully integrated DRAMsim into a variety of simulators including MASE, Sim-alpha, BOCHS, and GEMS. The simulator can be downloaded from www.ece.umd.edu/dramsim, and it is described in the following articles:

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Contact Information

Prof. Bruce Jacob - email address -

Traditional correspondence can be sent to

Prof. Bruce Jacob
Dept. of Electrical & Computer Engineering
University of Maryland
College Park, MD 20742

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