<pre>
/*
/* A Simple 32-bit Computer
/* HXC-32
/* (MicroProgram Implementation)
/* Brought to you
/*
/* By
/*
/* YOUR VERY OWN ENEE350 INSTRUCTOR
/*
/* This computer program simulates the fetch,decode
/* and execute cycles of a simple 32-bit computer
/*
/*
/* HXC-32 has the following registers:
/*
/*
/* A: 32 bits
/* B: 32 bits
/* MDR: 32 bits
/* MAR: 24 bits
/* IR: 32 bits
/* PC: 24 bits
/*
/* Its instruction repertoire consists of the following instructions
/*
/* Register Instructions
/* CLA: Clear A Opcode: 0000 0 0 ----- A = 0 HexCode: 00
/* CLB: Clear B Opcode: 0000 0 1 ----- B = 0 HexCode: 04
/* INA: Incre A Opcode: 0001 0 0 ----- A = A+1 HexCode: 10
/* INB: Incre B Opcode: 0001 0 1 ----- B = B+1 HexCode: 14
/* CMA: Compl A Opcode: 0010 0 0 ----- A = ~A HexCode: 20
/* CMB: Compl B Opcode: 0010 0 1 ----- B = ~B HexCode: 24
/* ORA: Or A,B Opcode: 0011 0 0 ----- A = A | B HexCode: 30
/* ORB: Or B,A Opcode: 0011 0 1 ----- B = A | B HexCode: 34
/* ANA: And A,B Opcode: 0100 0 0 ----- A = A & B HexCode: 40
/* ANB: And B,A Opcode: 0100 0 1 ----- B = A & B HexCode: 44
/* ADA: Add A,B Opcode: 0101 0 0 ----- A = A + B HexCode: 50
/* ADB: Add B,A Opcode: 0101 0 1 ----- B = A + B HexCode: 54
/* SRA: Shfr A Opcode: 0110 0 0 ----- A = A >> 1 HexCode: 60
/* SRB: Shfr B Opcode: 0110 0 1 ----- B = B >> 1 HexCode: 64
/* SLA: Shfl A Opcode: 0111 0 0 ----- A = A << 1 HexCode: 70
/* SLB: Shfl B Opcode: 0111 0 1 ----- A = A << 1 HexCode: 74
/*
/* Memory Reference Instructions
/*
/* CLM: Clear M Opcode: 0000 1 - ----- M = 0 HexCode: 08,09,0A
/* INM: Incre M Opcode: 0001 1 - ----- M = M+1 HexCode: 18,19,1A
/* CMM: Compl M Opcode: 0010 1 - ----- M = ~M HexCode: 28,29,2A
/* OMA: Or A,M Opcode: 0011 1 0 ----- A = M | A HexCode: 38,39,3A
/* OMB: Or B,M Opcode: 0011 1 1 ----- B = M | B HexCode: 3C,3D,3E
/* AMA: And A,M Opcode: 0100 1 0 ----- A = M & A HexCode: 48,49,4A
/* AMB: And B,M Opcode: 0100 1 1 ----- B = M & B HexCode: 4C,4D,4E
/* MAA: Add A,M Opcode: 0101 1 0 ----- A = M + A HexCode: 58,59,5A
/* MAB: Add B,M Opcode: 0101 1 1 ----- B = M + B HexCode: 5C,5D,5E
/* SRM: Shfr M Opcode: 0110 1 - ----- M = M >> 1 HexCode: 68,69,6A
/* SLM: Shfl M Opcode: 0111 1 - ----- M = M << 1 HexCode: 78,79,7A
/* LDA Load A,M Opcode: 1000 1 0 ----- A = M HexCode: 88,89,8A
/* LDB Load B,M Opcode: 1000 1 1 ----- B = M HexCode: 8C,8D,8E
/* STA Stor A,M Opcode: 1001 1 0 ----- M = A HexCode: 98,99,9A
/* STB Stor B,M Opcode: 1001 1 1 ----- M = B HexCode: 9C,9D,9E
/* Branch Instructions
/*
/* BAA: jmp Opcode: 1010 - - ----- PC=Br.Ad HexCode: A8,A9,AA
/* BPA: Br+ A Opcode: 1011 - 0 ----- PC=(A>0)&Br.Ad HexCode: B8,B9,BA
/* BPB: Br+ B Opcode: 1011 - 1 ----- PC=(B>0)&Br.Ad HexCode: BC,BD,BE
/* BZA: Br0 A Opcode: 1100 - 0 ----- PC=(A==0)&Br.Ad HexCode: C8,C9,CA
/* BZB: Br0 B Opcode: 1100 - 1 ----- PC=(B==0)&Br.Ad HexCode: CC,CD,CE
/* HLT Halt Opcode: 1101 - - ----- reset = 1 HexCode: D0
/* Operand or Branch address computation
/*
/* Immediate: MDR = IR[8:31]
/* Direct: MDR = MEM[IR[8:31]]
/* Indirect MDR = MEM[MEM[IR[8:31]]
/*
/* Programs are entered and displayed in hex code.
/*
/* Please communicate all your questions and comments to
/*
/* A. Yavuz Oruc
/* Professor
/* University of Maryland
/* College Park, MD 20742
/* E-mail: yavuz@eng.umd.edu
/*
/* November 1997
*/
#include "hexy32.h"
#include "hexy32mic.h"
#include
#include
#include
ENEE350Global g;
hxc32micglobal m;
void initialize (void);
unsigned long int EffOperand (void);
void main(void)
{unsigned long int address = 0, i = 0, j = 0; action = 0;
unsigned long int pcstr,location,location1,location2;
unsigned long int XBUS,YBUS,OBUS;
do
{ initialize();
g.reset = 0;
cout << "Type 0 to enter a program, 1 to display registers, 2 to display memory: ";
cin >> action;
cout << "\n";
if(action == 0)
{
cout << "Enter your program's starting address: ";
cin >> g.PC;
address =g.PC;
pcstr=address;
do
{cout << "Enter instruction " << address -g.PC << "\n";
cout << "Or type -1 to end your program: ";
scanf("%lX",&(g.MEMORY[address]));
address = address + 1;
}
while ( ((g.MEMORY)[address-1] != -1 ) && (address < 1024));
if (address >= 1024)
cout << "Memory overflow";
cout << "\nHere is your program: \n\n";
for (i = g.PC; i< address-1; i++)
{ cout << "Location " << i << ": "; printf("%08lX",g.MEMORY[i]); cout << "\n";}
cout << "\n Now load your data or type -1 to end your loading \n\n";
do
{cout << "Location: ";
scanf("%lX",&location);
if (location >= pcstr && location <= g.PC)
{cout << "Illegal location \n";}
else if (location != -1)
{
cout << "Data: ";
scanf("%lX",&(g.MEMORY[location]));
}
}
while ( location != -1 );
i = 1;
cout << "\nHere is the flow of execution of your program:\n\n";
while (g.reset == 0)
{cout << "Cycle " << i << ": ";
i= i+1;
cout << "\nHere is the current microcycle:\n\n";
j=1;
while (m.MIA < m.LastMicInst)
{
cout << "Micro-cycle " << j << ": ";
j= i+1;
m.MIR = MICROM[m.MIA];
m.MIA = m.MIA + 1;
switch(m.micopcode)
{
case 0://transfer
if (m.read == 1)
{
g.read = 1;
g.MDR = g.MEMORY[g.MAR];
g.read = 0;
}
switch(m.xbus)
{
case 0: XBUS = PC; break;
case 1: XBUS = MDR; break;
case 2: XBUS = A; break;
}
switch(m.ybus)
{
case 0: YBUS = IR; break;
case 1: YBUS = MDR; break;
case 2: YBUS = B; break;
}
switch(m.obus)
{
case 0: OBUS = XBUS; break;
case 1: OBUS = YBUS break;
case 2: OBUS = XBUS+1; break;
case 3: OBUS = YBUS +1; break;
case 4: OBUS = ~XBUS; break;
case 5: OBUS = ~YBUS; break;
case 6: OBUS = XBUS & YBUS; break;
case 7: OBUS = XBUS | YBUS; break;
case 8: OBUS = XBUS << 1; break;
case 9: OBUS = YBUS << 1; break;
case 10: OBUS = XBUS >> 1; break;
case 11: OBUS = YBUS << 1 break;
case 12: OBUS = XBUS + YBUS; break;
case 13: OBUS = XBUS + YBUS + cin; break;
case 14: OBUS = XBUS +~YBUS + 1; break;
case 15: OBUS = 0; break;
case 16: OBUS = 1; break;
case 17: //The obus values for 17-31 will be defined later on
}
switch(m.dest)
{
case 0: A = OBUS; break;
case 1: B = OBUS break;
case 2: MDR = OBUS; break;
case 3: MAR = OBUS; break;
case 4: IR = OBUS; break;
case 5: PC = OBUS; break;
case 6: m.done = OBUS;
break;
}
if (m.write == 1)
{
g.write = 1;
g.MEMORY[g.MAR] = g.MDR;
g.write = 0;
}
break;
case 1: //Branch
switch(m.branchsel)
{
case 0: if (g.C == m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 1: if (g.S == m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 2: if (g.V == m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 3: if (g.Z == m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 4: if ((g.opcode == 0) &&m.trubranch || (g.opcode != 0) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 5: if ((g.opcode == 1) &&m.trubranch || (g.opcode != 1) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 6: if ((g.opcode == 2) &&m.trubranch || (g.opcode != 2) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 7: if ((g.opcode == 3) &&m.trubranch || (g.opcode != 3) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 8: if ((g.opcode == 4) &&m.trubranch || (g.opcode != 4) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 9: if ((g.opcode == 5) &&m.trubranch || (g.opcode != 5) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 10: if ((g.opcode == 6) &&m.trubranch || (g.opcode != 6) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 11: if ((g.opcode == 7) &&m.trubranch || (g.opcode != 7) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 12: if ((g.opcode == 8) &&m.trubranch || (g.opcode != 8) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 13: if ((g.opcode == 9) &&m.trubranch || (g.opcode != 9) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 14: if ((g.opcode == 10) &&m.trubranch || (g.opcode != 10) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 15: if ((g.opcode == 11) &&m.trubranch || (g.opcode != 11) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 16: if ((g.opcode == 12) &&m.trubranch || (g.opcode != 12) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 17: if ((g.opcode == 13) &&m.trubranch || (g.opcode != 13) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 18: if ((g.opcode == 14) &&m.trubranch || (g.opcode != 14) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 19: if ((g.opcode == 15) &&m.trubranch || (g.opcode != 15) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 20: if (g.optype = m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 21: if (g.regtype = m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 22: if ((g.addrtype = 0) &&m.trubranch || (g.addrtype = 0) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 23: if ((g.addrtype = 1) &&m.trubranch || (g.addrtype = 0) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 24: if ((g.addrtype = 2) &&m.trubranch || (g.addrtype = 0) &&!m.trubranch) m.MIA = m.MIR &FFFF;
break;
case 25: m.MIA = m.MIR &FFFF; //Unconditional branch
break;
case 26:
break;
case 27:
break;
case 28:
break;
case 29:
break;
case 30:
break;
case 31:
break;
}
break;
case 2: //ROM transfer
break;
case 3: //Not used
break;
}
if (m.done == 1) m.MIA == 0;
}
cout << "A = "; printf("%08lX",g.A); cout << ", ";
cout << "B = "; printf("%08lX",g.B); cout << ", ";
cout << "Z = " << (short) g.Z; cout << ", ";
cout << "S = " << (short) g.S << "\n";
cout << "MAR = "; printf("%08lX",g.MAR); cout << ", ";
cout << "MDR = "; printf("%08lX",g.MDR); cout << ", ";
cout << "PC = "; printf("%08lX",g.PC); cout << ", ";
cout << "IR = "; printf("%08lX",g.IR); cout << ", ";
cout << "reset = " << (short) g.reset << "\n\n";
}
}
if (action == 1)
{
cout << "A = "; printf("%08lX",g.A); cout << ", ";
cout << "B = "; printf("%08lX",g.B); cout << ", ";
cout << "Z = " << (short) g.Z; cout << ", ";
cout << "S = " << (short) g.S << "\n";
cout << "MAR = "; printf("%08lX",g.MAR); cout << ", ";
cout << "MDR = "; printf("%08lX",g.MDR); cout << ", ";
cout << "PC = "; printf("%08lX",g.PC); cout << ", ";
cout << "IR = "; printf("%08lX",g.IR); cout << ", ";
cout << "reset = " << (short) g.reset << "\n\n";
}
if(action == 2)
{cout << "Enter the first address: ";
scanf("%lX",&location1);
// cin >> location1;
cout << "Enter the last address: ";
scanf("%lX",&location2);
// cin >> location2;
cout << "\n";
for (i = location1; i <= location2; i++)
{cout << "Location " << i << " : "; printf("%08lX",g.MEMORY[i]); cout << "\n";}
cout << "\n";
}
}
while (1);
}
</pre>