VLSI at the EE Department, University of Maryland, College Park

VLSI (=Very Large Scale Integrated) circuits are key to today's high technology. Students with a working knowledge of VLSI find themselves to be in high demand by industry.
Therefore it is the intent of the VLSI related faculty to make available to all students of the EE Department the chance to design, simulate, fabricate, and test VLSI chips. For students in our courses, funds for the fabrication of chips, particlarly Tiny Chips, are made available through NSF funding for fabrication via the MOSIS foundry (for which simulation and testing are required)

The steps to fabricate a chip are:
  1. Associated with a course authorized for fabrication money, arrange with the professor to get approval.
  2. Make a design and obtain a working simulation.
  3. Prepare a layout and obtain a CIF file from it.
  4. Contact Ms. Saroj Bhandari for authorization and procedures to send off the CIF file to MOSIS for fabrication (see below).
  5. Send the CIF file to MOSIS, correct errors, and obtain the clearance for fabrication from MOSIS. Typically it is eight weeks after the fabrication date when Ms. Bhandari receives the chips.
  6. Make measurements on the fabricated chip and send the report to MOSIS via Ms. Bhandari. This is a most crucial step as future funding depends on filing the report.

To process a chip through MOSIS, contact Ms. Saroj Bhandari.
Click here to send her email.

The activities are under the guidance of the EE Department MOSIS Group Committee comprised of Professors JaJa, Lin, Liu, Milor, Nakajima, and Newcomb. And recently NSF has made an equipment grant for the VLSI Design Automation Lab , through Professor K. Nakajima, to enhance our testing capabilities of digital chips. The faculty who have participated with their courses in which students recently have been able to fabricated chips are:

Both analog and digital circuits are under consideration with the activities including:

  • Digital
    For more information contact Professor K. Nakajima.
    Typical designs include RISC processors, DSP chips, low power CMOS chips, controllers, and A/D converters.

     Click here for the MOSIS information home page.

    Click here for the EE Department home page.

    For PSpice simulation evaluation files click here.

    This page's URL: http://www.ece.umd.edu/~newcomb/VLSI.html