ENEE244-020x: Digital Logic Design Fall 2026 Homeworks

• Homework 1, due via Canvas/ELMS submission on Sept. 11, 2026 at 11:59pm **Extended**. Exercises: 1.8, 1.10, 1.11, 1.16, 1.18 (use an 8-bit representation), 1.20 (use an 8-bit representation), 1.22, 1.24(b), 1.27. Please also answer the following question:

  In class we saw the [7,4]-Hamming code. Consider the analogous [15,11]-Hamming code.

  1. How many bits does it encode, and what is the length of the codeword?
  2. Give a parity-check matrix H for this code.
  3. Describe how to encode a message.
  4. Given a received word, describe how to decode it and correct a single-bit error.

• Homework 2, due via Canvas/ELMS submission on Sept. 23, 2026 at 11:59pm **Extended**. Exercises: 2.2(e),(f), 2.3(f), 2.4(e), 2.9(b),(c), 2.14(c),(d) [Draw the logic diagram], 2.16(a), *(b)* is extra credit. Hint for (b): Use induction on the number of variables to prove (b), 2.21, 2.29, 2.31. Please also answer the following question:

  Use Shannon's reduction theorem (in addition to other postulates and theorems of Boolean algebra) to simplify F where
  F(A,B,C) = A*(A'+B)*(A+C).

• Homework 3, due via Canvas/ELMS submission on Oct. 3, 2026 at 11:59pm
  Do the following exercises on don't care conditions and universal gates: hw_3_dc.pdf and the following exercises: 3.6(c),(d), 3.9 (e),(f), 3.12 (b), 3.13 (c), 3.15 (c) **use don't care conditions d(2,4,10) when solving this problem**, 3.16 (d), 3.19 (b), 3.20 (a), (b).
  

• Homework 4, due via Canvas/ELMS submission on Nov. 1, 2026 at 11:59pm
  Exercises 4.16, 4.17, 4.19, 4.21, 4.23, 4.27, 4.30, 4.32 (assume an 8x1 MUX), 4.33, 4.35(b).
  The following problems require Verilog coding and are extra credit (worth 10 points extra credit each): 4.36, 4.37.
  If you are submitting the extra credit, please upload a single .zip file named "Firstname_Lastname_HW4.zip" that contains the written homework solutions as well as two folders named Ex_4_36, Ex_4_37. Each folder should contain all your Verilog code (in a single .v file named module.v).
  For Exercise 4.36, your top-level module should be named "priority_encoder". The inputs should be named D[3:0] and the outputs should be named y, x, V (as in Figure 4.23).
  For Exercise 4.37, your top-level module shoud be named "adder_subtractor". The inputs should be named a[3:0], b[3:0], c_in, m, and the outputs should be named sum[3:0], c_out (similar to Figure 4.13 but without the "v" output.
  

• Homework 5, due via Canvas/ELMS submission on Nov. 8, 2026 at 11:59pm
  Do the following supplement as well as Exercises 5.1(a),(b),(c), 5.2, 5.3, 5.4(a),(d).